1. Field of the Invention
The present invention relates generally to a method of an IC layout and more particularly, to a method of common-centroid IC layout generation.
2. Description of the Related Art
In the analogous layout design, ratioed capacitors are frequently applied. The accuracy of capacitance ratios correlates closely with the matching properties among the ratioed capacitors and the induced parasitics resulting from interconnecting wires. However, most of previous works only emphasized the matching quality of a common-centroid placement but ignored the induced parasitics after it is routed.
U.S. Pat. No. 7,403,147 disclosed a capacitor array having an individual shielded unit capacitor and emphasized the common-centroid approach. However, it did not propose any solution to the induced parasitics after the wires are routed.
U.S. Pat. No. 7,992,117 disclosed a common-centroid layout and did not propose any solution to the induced parasitics after the routing is completed.